1. Field of the Invention
The invention relates to a failure analysis methodology; more particular, the invention relates to a method of detecting bitmap failure associated with physical coordinates.
2. Description of Related Art
In the IC manufacturing process, the continuously decreasing line width requires precise control and monitor of relevant devices. Based on the semiconductor technology in the nanometer generation, the devices must be accurately inspected and analyzed in order to increase the yield of the devices.
The existing methods of performing failure analysis on chips include bitmap failure detection whereby failure bits may be obtained and physically located; what is more, according to the failure item, the actual layer having the failure within the chip may be predicted.
The cause of bitmap failure is often unclear. To clarify the cause, the chip should be polished from the surface thereof to the layer possibly having the failure, and a scanning electron microscope (SEM) surface analysis is then performed on the layer. As a result, the bitmap failure analysis is labor-intensive and time-consuming.